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july 2004 1/19 ? VNQ660sp quad channel high side solid state relay (*) per each channel n output current per channel: 6a n cmos compatible inputs n open load detection (off state) n undervoltage & overvoltage n shut- down n overvoltage clamp n thermal shut-down n current limitation n very low stand-by power dissipation n protection against: n loss of ground & loss of v cc n reverse battery protection (**) description the VNQ660sp is a monolithic device made by using | stmicroelectronics vipower m0-3 technology, intended for driving resistive or inductive loads with one side connected to ground. this device has four independent channels. built- in thermal shut down and output current limitation protect the chip from over temperature and short circuit. type r ds(on) i out v cc VNQ660sp 50m w (*) 6a 36 v absolute maximum rating (**) see application schematic at page 8 symbol parameter value unit v cc supply voltage (continuous) 41 v -v cc reverse supply voltage (continuous) -0.3 v i out output current (continuous), per each channel internally limited a i r reverse output current (continuous), per each channel -15 a i in input current +/- 10 ma i stat status current +/- 10 ma i gnd ground current at t c < 25 c (continuous) -200 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=1.46mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =10a) 101 mj p tot power dissipation at t c =25 c 113.6 w t j junction operating temperature -40 to 150 c t stg storage temperature -65 to 150 c e c non repetitive clamping energy at t c =25 c150mj powerso-10 ? 1 10 order codes package tube t&r powerso-10 ? VNQ660sp VNQ660sp13tr rev. 2
2/19 VNQ660sp block diagram undervoltage overvoltage overtemp. 1 overtemp. 2 i lim2 demag 2 i lim1 demag 1 input 1 input 2 gnd v cc output 1 output 2 driver 2 driver 1 logic overtemp. 3 overtemp. 4 i lim4 demag 4 i lim3 demag 3 input 3 input 4 output 3 output 4 driver 4 driver 3 status status open load off-state current and voltage conventions i s i gnd v cc gnd input 4 input 3 i out2 i in3 i in4 v in4 v in3 v cc v out2 i out1 v out1 input 1 i in1 input 2 i in2 v in1 v in2 i stat status v stat output 4 output 3 i out3 i out4 v out4 v out3 output 1 output 2 v f1 (*) (*) v fn = v ccn - v outn during reverse battery condition
3/19 VNQ660sp configuration diagram (top view) & suggested connections for unused and n.c. 1 2 3 4 5 6 7 8 9 10 11 gnd output 4 output 3 output 2 output 1 status input 4 input 3 input 2 input 1 v cc thermal data (1) when mounted on a standard single-sided fr-4 board with 1cm2 of cu (at least 35 m m thick). horizontal mounting and no artificial air flow. (2) when mounted on a standard single-sided fr-4 board with 6cm2 of cu (at least 35 m m thick). horizontal mounting and no artificial air flow. electrical characteristics (v cc =6v up to 24v; -40 c 4/19 VNQ660sp electrical characteristics (continued) switching (v cc =13v) protections (per each channel) (see note 1) note 1: to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sig nals must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the durat ion and number of activation cycles. logic input (per each channel) openload detection (off state) per each channel (*) see figure 1 symbol parameter test conditions min typ max unit t d(on) turn-on delay time r l =13 w channels 1,2,3,4 40 70 m s t d(off) turn-on delay time r l =13 w channels 1,2,3,4 40 140 m s dv out /dt (on) turn-on voltage slope r l =13 w channels 1,2,3,4 see relative diagram v /m s dv out /dt (off) turn-off voltage slope r l =13 w channels 1,2,3,4 see relative diagram v /m s symbol parameter test conditions min typ max unit t tsd shutdown temperature 150 170 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 25 c i lim dc short circuit current 9v 5/19 VNQ660sp electrical transient requirements switching characteristics iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w iso t/r 7637/1 test pulse test levels result iiiiiiiv 1 cc cc 2 cc cc 3a cc cc 3b cc cc 4 cc cc 5 ce ee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 1 t t v load v in 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on) t r
6/19 VNQ660sp 2 truth table (per each channel) figure 1: status timing waveforms conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l v in v stat t dol openload status timing v in v stat overtemp status timing t sdl t sdl t sdl
7/19 VNQ660sp status input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc v cc >v ov status n input n status n undefined overtemperature input n status n t tsd t r figure 2: waveforms t j load voltage n v cc 8/19 VNQ660sp gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. application schematic v cc1,2 d ld +5v r prot status input1 +5v output3 output1 output2 output4 input3 input4 r prot r prot r prot r prot input2 m c gnd d gnd r gnd v gnd note: channels 3 & 4 have the same internal circuit as channel 1 & 2.
9/19 VNQ660sp load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w.
10/19 VNQ660sp high level input current input clamp voltage off state output current -50 -25 0 25 50 75 100 125 150 175 tc (o c ) 0 1 2 3 4 5 6 7 iih (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc (o c ) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vicl (v) iin=1ma input high level -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) input hysteresis voltage input low level -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vhyst (v) -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 1 2 3 4 5 6 7 8 9 10 il(off1) (a) off state vcc=24v vout=0v
11/19 VNQ660sp overvoltage shutdown turn-on voltage slope turn-off voltage slope i lim vs t case -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 34 36 38 40 42 44 46 48 50 52 54 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (o c) 0 50 100 150 200 250 300 350 400 450 500 dvout/dt(on) (v/ms) vcc=13v rl=13ohm -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 100 200 300 400 500 600 700 dvout/dt(off) (v/ms) vcc=13v rl=13ohm on state resistance vs t case on state resistance vs v cc -50 -25 0 25 50 75 100 125 150 175 tc (o c ) 0 2.5 5 7.5 10 12.5 15 17.5 20 ilim (a) -50 -25 0 25 50 75 100 125 150 175 tc (o c) 0 10 20 30 40 50 60 70 80 90 100 rds(on) (mohm) iout=1a vcc=9v; 13v; 18v 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 rds(on) (mohm) iout=1a tc=150oc tc=25oc tc= - 40oc
12/19 VNQ660sp status leakage current status low output voltage status clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 ilstat (a) vstat=5v -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 0.075 0.15 0.225 0.3 0.375 0.45 0.525 0.6 vstat (v) istat=1.6ma open load off state voltage detection threshold -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc ( oc ) 6 6.2 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 8 vscl (v) istat=1ma
13/19 VNQ660sp powerso-10 maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.01 0.1 1 10 100 l(mh) i lmax (a) a b c
14/19 VNQ660sp powerso-10 ? pc board r thj-amb vs. pcb copper area in open box free air condition powerso-10 ? thermal data layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: from minimum pad lay-out to 8cm 2 ). rthjamb (oc/w) 20 25 30 35 40 45 50 55 0246810 pcb cu heatsink area (cm^2)
15/19 VNQ660sp powerso-10 thermal impedance junction ambient single pulse 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) thermal fitting model of a single channel hsd in powerso-10 pulse calculation formula thermal parameter area/island (cm 2 ) 0.5 2 4 8 r1=r7=r9=r11 (c/w) 0.15 r2=r8=r10=r12 (c/w) 0.5 r3 ( c/w) 0.4 r4 (c/w) 10 r5 (c/w) 15 r6 (c/w) 26 14.5 10 6 c1=c7=c9=c11 (w.s/c) 0.0006 c2=c8=c10=c12 (w.s/c) 0.0021 c3 (w.s/c) 0.02 c4 (w.s/c) 0.5 c5 (w.s/c) 1.5 c6 (w.s/c) 5 10 14 18 z th d r th d z thtp 1 d C () + = where d t p t = 0.5 cm 2 2 cm 2 4 cm 2 8 cm 2
16/19 VNQ660sp 1 1 1 dim. mm. inch min. typ max. min. typ. max. a 3.35 3.65 0.132 0.144 a (*) 3.4 3.6 0.134 0.142 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 b (*) 0.37 0.53 0.014 0.021 c 0.35 0.55 0.013 0.022 c (*) 0.23 0.32 0.009 0.0126 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e2 7.20 7.60 0.283 300 e2 (*) 7.30 7.50 0.287 0.295 e4 5.90 6.10 0.232 0.240 e4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 f 1.25 1.35 0.049 0.053 f (*) 1.20 1.40 0.047 0.055 h 13.80 14.40 0.543 0.567 h (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 l 1.20 1.80 0.047 0.070 l (*) 0.80 1.10 0.031 0.043 a 0o 8o 0o 8o a (*) 2o 8o 2o 8o 1 1 powerso-10 ? mechanical data (*) muar only poa p013p detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a e c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
17/19 VNQ660sp powerso-10 ? suggested pad layout 1 tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0.54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b muar casablanca
18/19 VNQ660sp 1 1 1 revision history date revision description of changes jul 2004 1 - minor changes - current and voltage convention update (page 2). - configuration diagram (top view) & suggested connections for unused and n.c. pins insertion (page 3). - 6 cm 2 cu condition insertion in thermal data table (page 3). - v cc - output diode section update (page 3). - protections note insertion (page 4) - revision history table insertion (page 18). - disclaimers update (page 19). jul 2004 2 - disclaimers update (page 19). 1
19/19 VNQ660sp information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states http://www.st.com

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